Linear voltage regulators, including low dropout (LDO) regulators, use a pass device to provide a relatively constant voltage level to an output load. A control signal provided to a control terminal of the pass device determines the amount of current flowing through the pass device, so as to maintain the relatively constant voltage level. In a common implementation of an LDO regulator, the pass device is a p-channel metal-oxide semiconductor field-effect transistor (pMOSFET) and the control terminal is a gate of the pMOSFET. A typical linear voltage regulator also includes an error amplifier that generates the control signal based upon the difference between a reference voltage and a portion of the output voltage. As the output voltage decreases below a desired output voltage, the error amplifier and the pass device increase the amount of current flowing to the output load. As the output voltage increases above the desired output voltage, the current flow to the output load is decreased. In this way, a linear regulator uses a negative feedback loop to maintain the relatively constant voltage level provided to the output load.
The loop gain of a linear regulator as described above is frequency-dependent, and the linear regulator must be designed to ensure stability. The loop gain, and associated frequency and phase responses, of the linear regulator may be characterized using poles and zeros. The poles and zeros are determined from impedances within the linear regulator and associated circuitry, e.g., the output load and capacitor. In an ideal negative feedback system, the overall phase response is 180°, so that the feedback perfectly cancels the error at the output, e.g., the output voltage of a linear regulator. If the overall phase response approaches 0°, 360°, or a multiple thereof, the feedback becomes additive to the error, and the loop becomes unstable for gains greater than 0 dB. The loop stability is characterized using phase margin ϕM, which is the difference between 180° and the modulus of the critical phase ϕC, where the critical phase ϕC is the phase response at the frequency where the magnitude response is 0 dB, i.e., ϕM=180°−|ϕC mod 360°)|. Linear regulators having small but nonzero phase margins, e.g., <30°, are susceptible to excessive ringing in the output voltage when a load transient occurs. Larger phase margins, e.g, 45°≤ϕM≤60°, lead to faster settling of the output voltage after a load transient.
Each pole introduces a phase shift of −90°, whereas a zero introduces a phase shift of +90°. A linear regulator typically has at least an internal pole and a pole associated with the output load and output capacitor. Compensation networks, which may introduce zeros or move the frequency of a pole, must often be designed into or added to a linear regulator, to ensure stable operation of the linear regulator, i.e., that adequate phase margin is achieved.
The pole associated with the output capacitor and the output load resistance presents particular difficulties, as the output load resistance effectively varies as the load current varies. This leads to a pole frequency that varies with current. Compensation networks to address such a varying pole frequency are typically designed to provide adequate phase margin over an expected range of load current. The resultant linear regulator may only be stable (have adequate phase margin) within a fairly limited current range.
Compensation networks are desired that provide stability for linear regulators over a wide range of output current.